In the fabrication of integrated circuits (ICs) or chips, vias or trenches are typically created in the substrate, such as a silicon wafer, for various purposes. The vias or trenches are formed by etching into the substrate. Deep trenches (DTs), for example, serve as trench capacitors for an array of memory cells.
Conventionally, DTs are formed by first providing a pad stack over the surface of the wafer. The pad stack includes, for example, sequential layers of a pad oxide and a pad nitride. Above the pad stack is a hard mask layer comprising, for example, TEOS. The hard mask layer serves as a hard etch mask used to form the DTs.
A photoresist layer is deposited over the hard mask and patterned to selectively expose areas in the array region where the DTs are to be formed. Typically, the exposed regions of the hard mask, along with the pad stack below, are removed by a reactive ion etch (RIE) to expose the wafer. The photoresist is removed, and the exposed wafer regions are etched by RIE to create the DTs.
Conventional techniques for forming the hard mask layer result in uneven coverage of the hard mask material on the wafer. In particular, less material covers the edges and sides than the other regions of the wafer. As a result, the hard mask at the edges and sides is eroded away during the latter stages of the DT etch, exposing the pad stack beneath. This in turn causes the pad stack to be eroded away, exposing the wafer surface underneath. As the DT etch continues, formation of needle type surface at the exposed regions of the wafer results. Such needle type surface is referred to as "black silicon." A description of black silicon can be found in, for example, V. W. Hess, Solid State Technology, April 1981, p. 192 and G. K. Herb, Solid State Technology, October 1989, p. 104, which are hereby incorporated by reference for all purposes.
Black silicon forms because oxide islands are left on the wafer surface during DT etch. The oxide protects the underlying silicon from being etched. As such, the portions unprotected by the oxide continue to be etched, while the protected portions remain. As the RIE proceeds, the protected portions results in the formation of needles or spikes.
The formation of black silicon during RIE creates difficulties in the handling of the wafer. For example, the black silicon spikes are easily broken off and can adversely impact manufacturing yield.
One conventional technique of preventing the formation of black silicon is to employ a clamp ring to cover the wafer edge, protecting it during hard mask open RIE. However, the use of the clamp ring causes clamp finger shadowing, which affects lithographic resolution or reliability and etch uniformity. As a result, chip yield is reduced. Additionally, the use of the clamp ring prevents the use of electric static chuck (ESC) equipped tools, which are required in high density plasma etch tools.
From the foregoing discussion, it is desirable to provide an improved technique of fabricating semiconductor devices without the formation of black silicon.